When transmitting data over wireless channels, errors will be introduced due to, for example, variations in the received signal quality. Wireless modems typically use forward error correction (FEC), where redundancy is incorporated in the transmitted signal by including parity bits calculated from the transmitted information bits according to a coding scheme. Therefore, the number of bits transmitted over the channel is larger than the number of information bits.
Another way to protect against transmission errors is to use an automatic repeat request (ARQ) scheme in which a receiver uses an error detection code, such as a cyclic redundancy check (CRC), to detect if a data packet is received correctly or not. If no error is detected, the receiving equipment sends a positive acknowledgement (ACK) to the sender of the data packet. On the other hand, if an error is detected, the receiving equipment sends a negative acknowledgement (NACK) to the sending equipment, which then retransmits the data packet.
The Long Term Evolution (LTE) communication standard, and many other digital communications standards such as the Universal Mobile Telephone Standard (UMTS) and the Code Division Multiple Access 2000 (CDMA2000) standard, use a combination of FEC and ARQ called hybrid ARQ (HARQ) with soft combining. In HARQ with soft combining, the energy in all transmissions of the same transport block is employed, each transport block comprising one or more code words. This means that an incorrectly received transport block needs to be stored in a buffer at the receiving equipment until the retransmitted transport block arrives. Both the initial and retransmitted transport blocks are then combined to obtain a single transport block that can be decoded with greater reliability than the initial or retransmitted transport block alone. The HARQ is asynchronous, meaning that the time interval between different transmissions of the same transport block may vary. The FEC that is used in LTE typically employs turbo codes, and the hardware that performs decoding is typically referred to as a turbo decoder. A turbo decoder employs soft data bits for the decoding, where a soft data bit comprises an indication of whether a received data bit is determined to be a binary one or zero, and an indication of reliability of that determination.
For example, a soft bit may be represented by an integer, INT, in the range −32 to +31, where a positive value indicates a binary one and a negative value indicates a binary zero, and the magnitude of the integer indicates a reliability of the soft bit. In particular, a value −32 of the integer of may mean that it is very likely that the received data bit was transmitted as a binary zero, that is, the received data bit is a binary zero having a high reliability, and a value of 31 of the integer may mean that it is very likely that the received data bit was transmitted as a binary one, that is, the received data bit is a binary one having a high reliability. A range of integers −32 to 31 requires six binary values to represent each integer, and therefore, each soft bit requires six memory cells to represent each received data bit. Each of the integers may correspond to a log-likelihood ratio (LLR) value.
The memory for the HARQ buffer can typically be Static Random Access Memory (SRAM) on the same integrated circuit chip as signal processing functionality, or Synchronous Dynamic Random Access Memory (SDRAM) on a different integrated circuit chip to the signal processing functionality. On-chip SRAM is fast, but is also typically small and expensive. So, for bad wireless channel conditions, where a lot of HARQ buffer memory is needed, on-chip SRAM might not provide enough memory at an acceptable cost. In this case the HARQ buffers can be placed in an external SDRAM. Each memory cell in an SDRAM comprises a capacitor that can be either charged or discharged to represent a binary value. As time passes, the charge in the capacitor leaks away. To overcome this leakage, the SDRAM is typically refreshed periodically, meaning that the binary value is read from each memory cell and then rewritten again to restore the charge of the capacitor to its original level. For a typical Low Power Double Data Rate 2 (LPDDR2) memory, a refresh occurs at intervals denoted tREFI in the standard JESD209-2B published by the JEDEC Solid State Technology Association. For a 1 Gbit density SDRAM at a temperature up to 85° C., tREFI is 7.8 μs. Such a memory is arranged as 8192 rows, with all memory cells in a row being refreshed simultaneously, and with each row being refreshed each 8192×7.8 μs=64 ms. For a temperature above 85° C., tREFI is decreased to 7.8 μs/4=1.95 μs. In this case, each row will be refreshed each 16 ms. Each refresh will consume energy. The refreshing also interferes with memory access, because no data can be transferred to or from the memory while the memory is being refreshed, thereby increasing latency. The average latency for reading memory when no refreshing is taking place is typically 20 ns. However, the time required to refresh one row is typically 130 ns, so every 7.8 μs access to the memory is blocked for 130 ns, at temperatures up to 85° C. In the present disclosure, memory storage that is subject to leakage of stored information is referred to as a leaky.
Typically, the majority of the retransmissions will occur before the memory cells need to be refreshed. However, when the HARQ with soft combining is asynchronous, as in the case of LTE, the retransmission can occur at any time. In particular, the delay following a NACK before a retransmission from a communication network can take place may depend on the network configuration and current network loading. Moreover, the delay may be longer for networks operating in a time division duplex (TDD) mode, rather than a frequency division duplex (FDD) mode, due to the separation in the time domain of uplink and downlink time slots.